1. Field of the Invention
The present invention relates to an exposure apparatus, a method of controlling the same, and a method of manufacturing a device.
2. Description of the Related Art
In recent years, ultrafine patterning techniques as techniques of manufacturing a semiconductor device have been making remarkable progress. In photopatterning techniques in particular, it is usual for a reduction projection exposure apparatus (stepper) having a submicron resolution to be used; so, for example, the numerical aperture (NA) of an optical system is increased, and the exposure wavelength is shortened to further improve the resolution. For example, as the exposure wavelength shortens, exposure light sources are shifting from g- and i-line high-pressure mercury lamps to KrF and ArF excimer lasers. However, as exposure light shifts to short-wavelength light emitted by, for example, a KrF excimer laser, the usable glass material is limited, so it becomes difficult to correct chromatic aberration for the alignment wavelength of a projection exposure optical system. Hence, the recent reduction projection exposure apparatus is required to adopt an off-axis alignment detection system (OA detection system) free from the influence of the chromatic aberration of a projection exposure optical system.
On the other hand, not only conventional IC chips including a memory and logic, but also recent special devices including a MEMS and CMOS are manufactured as applied products using a conventional semiconductor exposure apparatus. However, devices including a MEMS are different from IC chips in several respects. Devices including a MEMS are different from IC chips in that, for example, the former is required to attain a relatively low line width resolution and overlay accuracy but a relatively large depth of focus.
Also, a special exposure process of forming an alignment mark on the lower side of a silicon wafer, and exposing the upper side of the silicon wafer upon alignment with reference to the alignment mark must be done. This process is executed when, for example, a through-hole via is formed to extend from the upper side of a wafer, and used to electrically connect the upper side to a circuit pattern on the lower side. As a method of detecting an alignment mark formed on the lower side of a wafer, Japanese Patent Laid-Open No. 2002-280299, for example, discloses a lithography apparatus which performs alignment using a detection system arranged on the lower side (wafer chuck side). However, in the method of arranging a detection system on the wafer chuck side, only an alignment mark at a position opposite to a specific position of a wafer chuck is an object to be measured. That is, the measurement position is limited, so an alignment mark formed at an arbitrary position on the lower side of the wafer cannot be measured.
To solve this problem, a method of measuring an alignment mark on the upper side of a silicon wafer by an OA detection system including a light source that emits infrared light, using the property that silicon is transparent to infrared light (wavelength: 1,000 nm or more), is available. In lower surface alignment in which silicon has a given thickness from the wafer surface to an alignment mark, variations in tilt of, for example, a wafer table or chuck with respect to the wafer surface may occur due to variations in thickness of the silicon wafer, and variations in overlay accuracy. It has been pointed out that in conventional techniques, the detection accuracy degrades upon a tilt of, for example, the wafer table or chuck.
More specifically, as has been reported conventionally, in a measurement technique such as an interferometer, a shift occurs in position to be exposed, when a wafer is exposed in a tilted state. Japanese Patent Laid-Open No. 5-315221, for example, discloses a method of detecting the tilt of an interferometer mirror, detecting the tilt of a wafer by a tilt measurement device, and calculating the amount of flexure of a table due to its self weight, thereby calculating an Abbe error. With this method, the amount of tilt of the wafer is added to the correction items of the Abbe error to measure the alignment mark with high accuracy. Also, Japanese Patent Laid-Open No. 2003-203842 discloses an arithmetic unit which calculates an error of a plane mirror for each position of a stage, and a method of driving the stage upon correcting the amount of tilt in accordance with the position, to which the stage moves, based on the error obtained by the arithmetic unit in advance.
A shift may occur in position to be exposed, during exposure when the tilt of the wafer surface changes upon lower surface alignment in which silicon has a given thickness from the wafer surface to an alignment mark, or in the interval between the alignment time and the exposure time if a thick resist is used. That is, when tilt correction is performed so as to reduce the tilt of the resist surface in exposure, a shift (shift error) may occur between a position to be ideally exposed and an actually exposed position. To attain exposure with a higher accuracy, a challenge associated with shift error correction is posed, but the conventional literatures describe no shift error correction methods.
FIGS. 12A and 12B are views for explaining a shift error that occurs in the interval between the alignment time and the exposure time, in which FIG. 12A shows an alignment state, and FIG. 12B shows an exposure state. Referring to FIG. 12A, an off-axis alignment detection system (OA detection system) 24 detects an alignment mark WM. Referring to FIG. 12B, a circuit pattern image of a mask (not shown) is transferred onto a wafer W via a projection optical system 22. The tilt of the wafer surface is different between the alignment state (FIG. 12A) and the exposure state (FIG. 12B).
The wafer W is set on a wafer chuck 51, and the alignment mark WM is formed on the surface of the wafer W, as shown in FIG. 12A. Also, the surface of the wafer W is coated (dispensed) with a resist 50. The thickness of the resist 50 on the wafer W is not uniform, but varies along the surface of the wafer W. For example, the thickness of the resist 50 on the right end side of the surface of the wafer W is defined as T1, and the thickness of the resist 50 on the left end side of the surface of the wafer W is defined as T2 (T2>T1). FIG. 12A assumes that the surface of the resist 50 has tilted with respect to an optical axis 1201 of a position detection system in wafer alignment (the surface of the resist 50 is not perpendicular to the optical axis of alignment). Although FIG. 12A shows an exemplary state in which the tilt of the surface of the resist 50 changes linearly, the definition of a shift error is not limited to this example.
On the other hand, FIG. 12B shows the state in which wafer surface measurement is performed at an exposure position, the tilt of the wafer surface is corrected, and exposure is performed. Upon tilt correction, the surface of the resist 50 becomes perpendicular to the optical axis of the projection optical system 22. As can be seen from FIG. 12B, due to the difference in tilt of the wafer surface from the alignment state, the alignment position set during the alignment time shown in FIG. 12A shifts during the exposure time shown in FIG. 12B. A shift between the position in alignment and that in exposure becomes a shift error.
FIGS. 13A to 13C are views for explaining the case wherein exposure is performed using a method which does not perform shift error correction. FIG. 13A shows the state before alignment, FIG. 13B shows the state in which the tilt of the wafer surface is corrected, alignment is performed, and exposure is performed in this state, and FIG. 13C shows the state after exposure. An example shown in FIG. 13A assumes that the surface of the resist 50 has tilted with respect to a wafer surface on which an alignment mark WM1 is formed as an alignment reference. As shown in FIG. 13B, even if tilt correction is performed, and alignment is performed so as to match the optical axis of the projection optical system 22 (FIG. 12B) with the alignment mark WM1, an alignment mark WM2 at an actually exposed position shifts with respect to a position RP to be exposed. That is, a shift error (shift) occurs, as shown in FIG. 13C. This means that when a surface layer to be exposed has tilted with respect to a layer serving as an alignment reference, in which the alignment mark WM1 is formed, a shift error occurs even if the tilt of the wafer surface is corrected, as shown in FIG. 13B.
As a method of solving the above-mentioned problem, a method of preventing a change in tilt of the wafer surface between the alignment measurement time and the exposure time so that a circuit pattern layer in which an alignment mark to be measured becomes parallel to the tilted wafer surface is available. However, when a bond wafer as mainly used in, for example, lower surface alignment is used, it is necessary to adhere a support substrate to a substrate on which a circuit pattern layer is formed, so the flatness of the substrate may degrade.
Also, to polish the substrate so that the circuit pattern layer becomes parallel to the tilted wafer surface, this must be done while measuring the circuit pattern layer and the wafer surface, so the yield may lower due to increases in cost and number of manufacturing steps.